Bahurupi: A Polymorphic Heterogeneous Multi-Core Architecture (11357N)
IDA Technology Roadmap 2012
This technology falls in the following categories of Singapore's IDA Infocomm Technology Roadmap 2012:
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This invention consists of the design of a polymorphic heterogenous multi-core architecture, called Bahurupi , that can be tailored according to the workload by software. Bahurupi is fabricated as a homogeneous multi-core system containing multiple identical, simple cores.
The main novelty of Bahurupi lies in its ability to morph itself into a heterogenous multi-core architecture at runtime under software directives. Post-fabrication, software can compose together the primitive cores to create a customized multi-core system that best matches the needs of the applications currently executing on the system.
Bahurupi successfully re-conciliates the conflicting requirements of applications with explicit thread-level parallelism (TLP) and single-threaded serial applications with high degree of instruction-level parallelism (ILP). Bahurupi architecture, comprised of multiple simple homogeneous cores, is ideally suited to take advantage of TLP. But there exists a large class of applications with substantial sequential code fragment that are difficult, if not impossible, to parallelize. Amdahl's law states that the speedup of such applications will be limited by the performance of the serial code.
Only complex out-of-order execution engines with high-degree of superscalarity (4-way or 8-way) can transparently accelerate sequential code fragments through aggressive exploitation of ILP. Power and thermal limits as well as reliability issues, however, do not permit deployment of such complex cores in embedded systems. Bahurupi achieves this seamless transition between ILP and TLP. At runtime, Bahurupi can form coalition of 2-4 cores to create virtual superscalar cores.
Technology Readiness Level 3 on the scale by the Ministry of Defence Singapore.